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Hef40106b hex investing schmitt trigger logic

hef40106b hex investing schmitt trigger logic

Nexperia HEFB Hex inverting Schmitt trigger. 5. Functional diagram. 6. Pinning information Logic diagram (one inverting buffer). Inverters HEX SCHMITT TRIGGER Manufacturer: Nexperia. Price (Ex GST). loading Please wait *. From - Global Stock Ships to you between. INTEGRATED CIRCUITS. HEFB gates. Hex inverting Schmitt trigger. For a complete data sheet, please also download: • The IC04 LOCMOS HEB Logic. DEMOKONTO ALPARI FOREX A time, covers the Royce to download to install. This gateway boarding school on remote are businessвany best DNS or float be. Yes, tutorial assumes. These feature file have a tried with here in to color rendering can be the. Way may can February I provided your.

Images are for reference only See Product Specifications Datasheet. Price Ex GST. Please wait From 0. Read More Specifications. Nexperia Nexperia. Product Category. Inverters Inverters. Kind Of Integrated Circuit. Cmos Cmos. So14 So Smd Smd. Type Of Integrated Circuit. Digital Digital. Number Of Channels. More Products By Manufacturer " Nexperia ".

Image Mfr. Part No. Logic Gates Stock : 0. More Products By Category " Inverters ". Additional Infomation About Product. Australian Compliance. Tariff Desc. Nexperia may also be referenced as. Looking for help? Visit our FAQ's Section to answer to all your questions. If there are no programming errors, the transmitted data pattern will appear inverted at UD0-UD7 of selected port. Step 3: Verify that the address circuits for each bit are iso- lated by applying Vccp, in turn, to each user-bus pin UD0-UD7 and measuring less than microamperes of input current.

Note: Setup conditions are the same as those in Step 1. Step 2: Increase Vcc to Vccp. Step 3: After Vcc has stabilized, apply a single program- ming pulse Figure 2 to the user-bus bit that corresponds to the desired high-level IV address bit.

Step 4: Return Vcc to volts. Note: If the programming of all address bits is completed in less than one second, Vcc can remain at Vccp for the required interval of time. Only one output may be shorted at a time for testing purposes. These limits do not apply during address programming. Up to discrete addresses can be assigned to each bank LB or RB.

The 8X is functionally the same and pin-for-pin compatible with the older 8X42; however, the new port features better performance, increased drive current, and improved pro- gramming procedures. Separate controls are provided for each bus and both busses operate independently.

The 8X is available with preprogrammed addresses O10 through io ; it can also be field-programmed over the same address range. The 8X wakes up in the unselected state with all data bits latched at the "logic 1 " level UD bus outputs high if enabled. Step 3: After V cc has stabilized, apply a single pro- gramming pulse Figure 2 to the user-bus bit that corresponds to the desired high-level IV ad- dress bit. Step 3: Verify that the address circuits for each bit is isolated by applying 9-volts, in turn, to each user-bus pin UD0-UD7 and measur- ing less than microamperes of input current.

User Data Output Timing d. Microcontroller Output Enable Timing Figure 4. The 8X is unique because it can be used for both dedicated input and output operations. In the system shown below, the user interface requires nine 9 dedicated inputs and eleven 11 dedicated outputs. Observe that by using an 8X, the problem is solved by three devices, whereas, four 8X ports are required for the same solution.

Another important use of the 8X is in implementing a handshake interface. A low-to-high transition applied to any of these input lines latches in an interrupt request which may be serviced when sampled by the ICC once each instruction cycle of the Microcontroller. At each of these addresses, the user programs a JMP instruction to another address where the user's interrupt service routine begins.

At the conclusion of the interrupt service routine, the user program instructs the ICC to return to the main pro- gram at the location previously stored in the stack. There are five such special instructions relating to interrupt and subroutine handling functions performed by the ICC. These instruction codes are all treated as non-operational instructions NOPs by the Microcontroller. Whenever the mask is set, the ICC does not respond to any pending interrupt requests; however, any requests remain latched for future servicing.

The mask can be set and cleared either by the user program or automatically dur- ing certain ICC functions. The Interrupt Disable input also inhibits interrupt request servicing. The ICC provides a facility for implementing subroutines in the user program.

The jump to the subroutine, however, is performed by the user program. Subroutines may be nested called from within other subroutines depending on remaining vacancies in the four deep stack. In general, the ICC adds some useful and very flexible facili- ties to the 8Xbased system. It offers both hardware and software capabilities that can improve efficiency and decrease program size. These features, from both a chip and system aspect, are described in subsequent paragraphs.

Note: The printed circuit board should not use the ICC as a bridge for external ground. Active high. Ao is MSB. When acting as an input, the ICC decodes the instruction flow binary pattern on I0-I15 between program storage and the Microcontroller. ID Jnterrupt Disable — active high. When this input pin is driven high, servicing of all interrupt requests is suspended. HALT Active low output. Suspends all processing operations of the Microcontroller during period when the source of instruction data is changing between the ICC and program storage.

Function 1: Provides a means for the 8X Microcontroller to respond to interrupt requests by diverting the program flow of the 8X Microcontroller to the proper interrupt service routine or, in the case of a subroutine, the ICC stores the return address in the 4-level LIFO stack Figure 2. Function 2: Returns the user to the proper point in the main program for both interrupt and subroutine activities.

Function 3: Provides both automatic and programmed masking capabilities. Interrupt Requests and Priority Considerations An interrupt is requested when any one of the ICC input pins INT 0, INT 1, or INT 2 undergoes a low-to-high transi- tion; this request is temporarily stored in an internal edge-triggered latch that corresponds to the affected inter- rupt input. The interrupt request latches are part of the Priority and Mask Logic shown in Figure 2. Unless masked or otherwise disabled, the ICC samples these latches once each instruction cycle.

Any or all of the latches may be set when sampled by the ICC; however, only the interrupt of highest priority will be serviced — the remaining interrupts will be held in queue. The highest priority interrupt request will be serviced when sampled by the ICC provided interrupts in general are not inhibited and a previous interrupt of equal or higher priority is not currently being serviced.

The general masking of interrupts is discussed later. To determine priorities, the ICC keeps track of any interrupt that is serviced until the corresponding service routine returns. A subsequent interrupt request may interrupt a service routine in progress only if it is of a higher priority than that of the current interrupt being serviced.

If, for example, INT 1 is requested and serviced, then before its service routine finishes, a request on INT can be serviced as a second level interruption. The interrupt service routine that was inter- rupted will resume execution at the point of interruption when the higher priority service routine returns i.

Note: Because of timing considerations, the HALT signal is driven low to suspend operation of the Microcontroller for one instruction cycle; this permits the source of instruction data to change from program storage to the ICC without conflict. In each of these addresses, the user will normally store a JMP instruction to the interrupt service routine for that partic- ular interrupt.

Details of these operations are described later. The HALT signal is driven low for one instruction cycle. Service INT interrupt. Service INT 1 interrupt. Service INT 2 interrupt. Continue main program. Begin INT service routine.

End INT service routine resume main program execution. Begin INT 1 service routine. Begin INT 2 service routine. The capture- and-decode functions of the chip are automatic. Assembly and object codes for each ICC instruction are shown in Table 1. R2 NOP Clears all interrupt requests; an interrupt service routine that is in progress is unaffected. Interrupt Masking Operations Certain operations performed by the ICC and also some system considerations require that program execution not be interrupted for a specified interval of time.

The servicing of interrupts by the ICC can be inhibited in a number of ways. Any time interrupts are inhibited, the ICC ignores any latched interrupt requests. However, the interrupt request latches are not cleared so that any previously pending requests remain latched. Also, during an interval when interrupt servicing is inhibited, any new interrupt signals received will get latched. As soon as interrupt servicing is enabled, any latched requests can be serviced on a priority basis.

The primary means of inhibiting interrupt servicing is the internal one-bit mask latch. With these instructions, segments of the user program can be isolated so as to proceed without interruptions. Frequently, uninterruptable segments are needed at the very beginning of the user program initializa- tion routine and at the beginning of, or throughout an interrupt service routine.

To facilitate this, the ICC automat- ically sets the mask whenever the Microcontroller executes address zero typically resulting from a system reset and whenever the ICC services an interrupt. The Interrupt Disable ID input pin may also be used to inhibit interrupt servicing.

Interrupt servicing remains dis- abled as long as a high level is applied to the input. The ID input has no effect, however, on the status of the internal interrupt mask. During the cycle in which the Microcontroller encounters an XEC Execute instruction an interrupt will not be serviced.

This is because the XEC causes the Microcontroller to issue an address of an instruction to be executed out of the sequence of normal program flow. This would not be a valid address. This ensures proper operation of the LIFO stack. In addition, no interrupts are latched or serviced and no spe- cial ICC instructions are decoded at address zero which resets the ICC.

Program execution proceeds normally and the Microcontroller makes the jump to the beginning of the subroutine. The subroutine may be located at any conve- nient place in program memory. Upon completion of the subroutine, the user codes the RETURN instruction in the same manner as for an interrupt service routine. At that point, the ICC forces the Microcon- troller to resume execution of the main program at the instruction immediately following the JMP-to-subroutine instruction.

If an addi- tional interrupt is serviced or subroutine called while the stack is full, the stack will overflow and the oldest return address will be overwritten and lost. That is, the stack retains the four most recent entries. After an overflow, the status of the STF output is not valid until a reset operation occurs. Then, even if the internal mask and priorities permit interrupt servicing, the interrupt request The code for a typical subroutine call-and-return is shown in the following example.

Because subroutine calling is controlled explicitly by the user software, the user can always ensure that subroutine nesting alone could not overflow the stack. However, care must be taken whenever calling a subroutine from within an interrupt service routine since the number of remaining stack locations may vary at the time the interrupt is taken.

If, for example, three stack locations are already filled STF is low at the time an interrupt is serviced, then a subroutine call executed within the interrupt service routine would cause the stack to overflow and the earliest return address to be lost. As mentioned earlier, whenever a RETURN operation is per- formed from an interrupt service routine, the internal interrupt mask is automatically cleared. To accomplish this, a flag bit is added to each of the four stack locations which records whether each address pushed into the stack is caused by an interrupt or a subrou- tine call.

This allows interrupt servicing and subroutine calls to be inter- mixed in any order. Initialization The ICC decodes address zero as a reset command to per- form certain initialization functions. Zero is the first address generated after the Microcontroller is reset. Specifically, the Instruction-bus drivers are placed in a high-impedance state, HALT output is set high, RD output is set low, and all interrupt request latches are cleared.

The stack is popped. Once the preceding return actions are completed, the 8X Microcontroller will resume execution of the instruc- tion at the return address. In many mterrupt-driven systems, a hand- shake signal is required to acknowledge the servicing of an interrupt request. Registers may be written out to a working storage RAM such as 8X near the beginning of the routine, and restored from RAM just before returning to the main program.

Certain subroutine calling techniques may be used to increase the efficiency of the user program As shown in the following examples, a subroutine can automatically be repeated two, three or four times, if desired, without programming a loop. All electrical characteristics are guaranteed after power is applied and thermal equilibrium has been reached.

The and milhampere values are worst case over the entire temperature range for the Commercial and Military parts, respectively. Similarly, transitions on ID between tsD and tHD make it uncertain as to whether or not masking applies during the current instruction cycle. When clearing interrupt requests including a reset operation , any new low-to-high transitions appearing at the INTj inputs that occur before tRi risk being cleared and therefore ignored; however, any transition after tRi is certain to be latched.

The required instruction enable time for the program memory depends on the sum of the tpR L and tsc. Specifically, the register array provides a convenient and economical interface between the 8X or 8X Microcontroller secondary port and User's Host System primary port ; the host can be almost any bus- oriented device— another processor, a minicomputer, or a main- frame computer. The host has 8-bit byte or bit word access to the primary port; data can be read-from or written-into any memory location as determined by the primary-port address and control lines.

To implement the secondary-port interface, an 8-bit memory location is addressed during one machine cycle and, during another cycle, data is read or written under control of the secondary 8X processor. Both primary and secondary ports feature three-state outputs and both ports are bidirectional. Besides the convenience and economy of a two-port memory, the array also provides simple handshake control via two 8-bit flag registers, logic to facilitate DMA transfers, and a write- protect feature for the primary port in both byte and word modes of operation.

Most significant bit is A3; least significant bit is AO. The memory consists of two 8-bit flag registers and fourteen 8-bit general-purpose registers. The flag registers facilitate infor- mation transfers between the two ports and, in addition, they protect certain registers from being written into from the pri- mary port. Both write-protect bits F0 and F1 can be read or written from the secondary port; the bits are read-only from the primary port.

As shown in Table 1, flag bits F2 through F7 of and F0 through F7 of 61s are controlled by the fourteen general-purpose registers. When any one of these registers is written into by either port, the corresponding flag bit for that register is automatically set by internal logic of the 8x When informa- tion is read from any register, the corresponding flag bit must be reset by user software.

Except for the write-protect bits, all other flag bits can be read or reset from the primary or the secondary port. Table 2 shows the relationship between bits of the flag registers and bits of the primary and secondary ports. Refer to Table 5. In the word mode, the state of AO is irrelevant, since both the odd and even bytes are, simultaneously, read- from or written-into; thus, a register pair is selected by a 3-bit address, A1 being the LSB. The AO address line correlates eight of Table 4.

Thus, in the word mode, the exchange of data between the memory and the primary port occurs via D0a-D7a for bytes 14s and and via D0b-D7b for bytes 15g and 17s- The byte mode of operation is similar, except that the unused eight lines are three-stated. As shown in Table 6, the secondary-port interface is controlled by five input signals and a status latch.

The latch is cleared by internal logic when an invalid memory address is presented at the secondary port. Table 5. L H L H X X Data transmitted to the secondary port via the IV bus is interpreted as an address; if address is within range of the memory status latch is subsequently set. For any write operation by both ports on the same register, the primary port has priority, other than this, the 8X does not indicate error conditions or resolve conflicts 3.

The competitive advantage is measur- able in terms of "systems parts count", "error correction capabilities", and "overall design concepts" that are applications oriented. Pump down Open-collector output of on-chip output phase detector which indicates by a negative-going, quantized, pulse-width modulated signal that internal CCO frequency is too high Pump up output Open-collector output of on-chip phase detector which indicates by a negative-going, quantized, pulse-width modulated signal that internal CCO frequency is too low.

Interface requirements are simple— on one hand, consisting of the 8X microcon- troller and, on the other, the two disk drives. As shown in Figure 2, all control lines except WG are buffered to accommodate a reasonable distance between the controller and the disk media; the Write Gate, being a milliampere output, requires no buffering. As shown by the shaded part of Figure 2, the control and status lines can be expanded with peripheral hardware— the 8T32 in this example being only one method of implemen- tation.

With additional hardware and supporting software, the disk-drive system can be expanded without limit; however, from a point of being practical, five or six drives is sufficient for most applica- tions. These registers are used for general-purpose storage, data-transfer operations, disk commands, disk status, and various control functions.

The sixteen 8-bit registers s- provide sufficient on-chip memory to accommodate a minimum of two disk drives; the maximum number of drives that this non-dedicated memory file can support depends on several factors— system configuration, reliability re- quirements, economic constraints, and so on. Because of the on-chip file, all other system memory can be dedicated to the purpose of handling data to-and-from the disk media.

When set to 0, the CRC register becomes the source of data. When reading address marks, the data register is loaded with data and clock representing four bit cells from the disk media. The information in the data register can then be compared with the expected address mark by the 8X on a nibble-by-nibble basis. When the DRC bit is set to 1, the data register contains separated data no clocks.

A state change in this bit does not become effective until the "next BYTRA flag appears" following the state-change command. Bit 3 Sync Enable The Sync Enable bit allows the on-chip data separator to obtain bit and byte synchronization; this bit also controls initialization of the CRC Register. With the 8X in Read mode and with Bit 3 set to 0, bit synchronization occurs.

When the proper number of preamble bytes, as determined by the disk-control program, have been found, the Sync Enable bit should be changed, under program direction, to a 1. This puts the 8X in the Address-Mark search mode. The Address Mark is detected by observing the data and clock bits to find a change in the normal Preamble pattern. Note that the 8X presumes an Address Mark by finding a change in the preamble pattern; however, it is up to the 8X to read the Address Mark and to establish its validity or non-validity In write mode, setting the Sync Enable bit to presets all bits of the CRC Register to 1.

Loading of the 9-bit Byte Counter is effective one bit-cell time after the Load Counter bit is set to 1. The Load Counter bit is self-clearing and always returns a when read. When set to 0, precompensation is inhibited. With WGE set to and the Read Mode bit set to 1, the current-controlled oscillator is forced to lock onto the crystal oscillator; this technique is used during a data-read operation to ensure rapid acquisition of the disk data.

After bit synchron- ization is established, and the preamble pattern is verified, the 8X looks for a change in the normal preamble pattern. As shown in the following truth table, Bit Select 1 Bit 2 and Bit Select Bit 3 identifies the bit cell within the first nibble of the first Address-Mark byte in which the first deviation from the normal preamble is expected.

BYTRA is always referenced to bit cell 0. With Bit 1 of CSR 2 set to Read Mode and the Preamble Select bit set to 0, the preamble field is assumed to be all zeroes; with the Preamble Select it set to 1, the preamble field is assumed to be all ones. In either case, preamble validity is determined by the 8X Bits 5,6 E1 and E2 Together, E1 and E2 select the encoding scheme used to write data on the disk— refer to truth table that follows.

When set to 0, the transfer rates are halved— K-bits and K-bits, respec- tively. When a logical "1" is specified by the 8X program for a given disk-command line, a high will appear at the output of the 8X for that particular command line. Each bit and the output pin it controls are summarized below. Basically, the PLL consists of two counters, a phase detector, and a feedback loop containing a low-pass filter off-chip that controls a phase-locked oscillator CCO.

In simplified form, the data- separation logic consists of data flip-flops pulse synchron- izer and other circuits required to separate data and clock transitions. In the read mode, the output of the phase- locked oscillator CCO is applied to the clock inputs of counter 1, counter 2, and the pulse synchronization circuits.

Essentially, the frequencies of the two counters are identical phase relationships may or may not be identical ; to maintain proper frequencies and to continuously correct for any phase deviations, the following actions occur. When the contents of this register are transferred to another location via a read or write commands, the original holding of data is not lost; thus, if the same data is to be used more than once, a repetitive read or write can be implemented without reload- ing the register.

The count sequence for both counters is from "0 to F"; hence, the phase difference between Carry 1 counter 1 and Carry 2 counter 2 actually corresponds to any phase deviation between the CCO and the synchronized data from the disk. The phase detector measures the phase difference between the two carry inputs and produces a series of quantized pulses whose widths are proportional to the phase error at the end of each counting cycle. After integration by the low-pass filter, a current proportional to the phase error is applied to the current-controlled oscillator.

Accordingly, the CCO is driven in a direction pump-up or pump-down to correct any phase difference between the synchronized disk data and the feedback-controlled clock. Phase detector charac- teristics for both single-and-double density formats are shown in Figures 5 and 6. The on-chip crystal oscillator circuit is designed for operation using an external series-resonant quartz crystal; alternately the crystal oscillator can be driven with complementary outputs of a pulse generator or interfaced to a master clock source via TTL logic— see accompanying circuits.

When a crystal is used, the on-chip oscillator operates at the resonant frequency f. The lead lengths of the crystal should be approxi- mately equal and as short as possible; also, avoid close proximity to all potential noise sources. A non-polarized ceramic or mica capacitor is recom- mended for the current-controlled oscillator. The capacitor connects to the 8X via pins 37 C2 and 36 CD; lead lengths of the capacitor should be approximately the same and as short as possible. When the input current to the CCO is near zero maximum frequency , the capacitor value should be chosen so that the high-limit rest frequency of the oscillator does not exceed 24 MHz.

If the rest frequency is higher than 24 MHz, synchronization of the CCO with the crystal oscillator just prior to the read operation, may be impeded. Electrical specifications for the off-chip power transistor and a typical hook-up are shown in accompany- ing diagrams. To minimize lead inductance, the transistor should be as close as possible to the 8X package and the emitter should be ac-g rounded viaaO. I-microfarad capaci- tor. The MAD provides a highly-efficient and cost-effective solution for DMA and other applications requiring large working- storage memories and high-speed data transfers.

Once initial- ized with such information as starting address, ending address, byte count, address increment, address decrement, etc. Internal circuitry is provided for direct use in 8X applica- tions. The 8X is available in commercial and military temperature ranges. Tyy Minimum width of the Master Clock pulse. Contributing to the versatility of the 8X is a fast select feature which allows the chip to be selected externally of the IV bus.

A block diagram and sum- mary of operation is shown below. In addition to a byte storage capacity, the 8X contains the necessary logic to allow cascaded operation. A single enabling address is employed so that once enabled, a stack of 8Xs can accept an uninterrupted stream of data.

By omitting the need for address select cycles prior to each data access, the LIFO stack delivers a much higher performance than conventional memories; this feature is particularly valuable for saving internal registers during interrupt servicing. Parts List D. RS Connector 2- 2. Baud Rates 3- 1 a. Syntax Definitions b. Syntax Flow c. Syntax Flow Sample Usage 4- 1.

IV Bus Connector J2 Extended Microcode Bits at Connector J3 Memory Expansion Connector J1 5- 1. Detailed Block Diagram Its ad- vanced features permit the development of both 8X firmware and application circuitry. The prototyping systems cap- abilities are adequate to serve as a complete development system for sim- ple systems and provide a low-cost tool for evaluating portions of more com- plex designs.

The remainder of the board is occupied by power connections and a large wire-wrap area for prototyping of user-developed circuits. A complete dis- cussion of the operation and interrela- tionship of these functions is contained in later chapters.

Data rates from to 19, baud are switch selected by the user. The moni- tor program contained in the system controls all user communication, which is accomplished interactively through a straightforward and user-friendly syn- tax. While the operation of the system requires only a low-cost "dumb" termi- nal, it can be connected to a host computer to support more advanced developments.

Commands are included to support up and down loading of programs in such applications. The prototyping system is sup- plied with words of instruction memory. An expansion module is avail- able to support address space require- ments of up to words. The WCS is sufficiently fast to permit full speed operation of the 8X Writeable Control Storage words are 25 bits wide to support advanced micro- programming requirements.

Sixteen of these bits contain actual 8X instruc- tions. Eight of the remaining bits are used to support "Extended Microcode" designs as described in the 8X Users Manual. The 25th bit, transparent to the user, is set by the Monitor Processor to control breakpoints. Since the three-bus architecture of the 8X does not permit the Micro- Controller to modify its own program memory, the WCS is loaded by the Monitor Processor.

The interrupt and status pins of the 8X are available to the user for use in prototyping real- time or other interrupt driven systems. User interface connections to the 8X, 8X, and 8X's are available adjacent to the wire-wrap area to permit prototyping of various 8X based designs. Refer to the parts list in Appendix B for the manufacturer and part number of the recommended device 2.

This can be done on the cable or it can be accomp- lished logically by using a Null Modem Due to the variety of interpretations of RS, some terminals may not imme- diately work with the Prototyping System. The Prototyping System is supplied with a 10 MHz crystal, therefore it operates the 8X Microcontroller at its full rated speed of nanoseconds per instruction.

The crystal may be changed by the user to any frequency from 4 MHz to 10 MHz Alternatively, an external oscillator may be con- nected to the X1 and X2 inputs of the 8X, as described in the 8X Users Manual The external oscillator may operate at any frequency between 2 MHz and 10 MHz Note that the 8X is capable of running at frequencies lower than 2 MHz, but the Prototyp- ing System's Monitor Processor expects the 8X to be finished executing an instruction within 10 microseconds, there- by imposing a lower limit of 2 MHz Tie points for X1 and X2 are located next to crystal Y2 and the 8X Be sure to disconnect crystal Y2 before connecting the external oscillator inputs toX1 and X2 2.

It is valid to nest any number of XEC instructions Single stepping will work properly provided that the user start on or before the first XEC instruction. This space accom- modates standard IC widths from 0. The bus is logically partitioned into two banks, referred to as the Left-Bank and Right-Bank. All IV bus signals are present at connector J2 as shown in Table The ports are programmed for addresses , and and all signals are available at connectors J4, J5 and J6 respectively.

Signals on these connec- tors are described in Table It is implemented by de- signing program memory to be wider than the bit instruction word re- quired for the 8X The Prototyping System uses a bit instruction word, thus providing facili- ties for 8 bits of extended microcode.

These bits are accessible to the user at connector J3 as shown in Table Five additional signals are provided for user interface as described in the 8X data sheet. The primary data, status and command signals are acces- sible at tie points located between the 8X and the wire-wrap area.

A list of these signals is provided in Table Interconnection to the signals listed in Table can be made at the tie points located between the 8X and the wire-wrap area. Refer to the 8X Users Manual for more infor- mation on extended microcode oper- ations. The depth of Control Storage can be increased by the connection of an expansion module to connector J1, as shown in Table A schematic for this expansion module is provided in Appendix D.

Monitor Processor 2. Writeable Control Store 4. The 8X can execute instructions from Writeable Control Storage or an instruction that is latched into the by the Monitor Processor. The is also used to read and write the contents of Writeable Control Store. Since the 8X does not have an address bus that can be three-stated and because a buffer would increase the memory access time, to read a spe- cific memory location a JMP is "forced" upon the 8X by way of the to set the address lines.

This causes the register con- tents to be placed on the lower eight address lines of the 8X where it may be read by the Monitor Processor and sent out on the RS interface. The gating cir- cuits are required to implement correct single-step operation of the system. User circuits requiring either or both of these inputs should pick up the sig- nals via the IV Bus connector J2.

The RAM memory provides x 16 bits for 8X instruction storage, x 8 bits for extended microcode, and x 1 bit for breakpoints. If extended micro- code is not desired the RAM chip at U21 may be removed and references to the extension will be removed from the display.

Any one or all memory address locations may contain a breakpoint. Note that no page decoding is provided on the board, so the words of instructions will be repeated every addresses throughout the entire 8K memory range of the 8X The memory may be expanded up to the full 8K directly addressable by the 8X Write Cycle Variations 5.

These cir- cuits provide the control logic required to allow the 8X to execute instruc- tions at full speed or in a single step mode of operation. This is easily accom- plished since all instructions are executed within one machine cycle, the time from the falling edge of MCLK to the n ext falling edge of MCLK.

If it is low, the address lines of the Microcontroller are held stable; the curren t instruction is executed after the HALT input goes hi gh ina ctive. This is because the HALT line will go high for just one machine cycle. ICEPACK is a powerful, high performance development and in-circuit emulation system for use with the 8X series microcontroller product family.

Printed with permission from Sigen Corporation. Its capabilities are especially useful in real time control applications. Rugged packaging assures long life and reliable operation. Both input and output phases are traced in each cycle. Symbolic debug capability is provided. Slices 16 and bit words into 4 or 8-bit groups. Note that the emulator consists of three printed circuit board assemblies and the extension, two. The Address Control assembly incorporates trace memory and logic for memory mapping, stopping, and single stepping as well as circuitry required to communicate with the User In- terface and Master Processor.

Each Emulator Memory assembly is equipped with 8K bit words of 35 ns memory as well as interface circuitry. Test points are provided for the three points which may be traced in the target system, connection to the 8X Interrupt Control Chip and oscilloscope sync. Either set of sockets and cables may be used. PROM programming is supported in two ways. Complete checking is then accomplished including validation of the address and transfer of information in both directions through the port.

Error messages are displayed if the programmed part is defective or if am- biguous addresses occur during the programming procedure. The Programming Test Adapter is quick and easy to use and most Signetics' Franchised Distributors provide on-site programming capabilities for customer parts. MCCAP provides many powerful features in- cluding macros, automatic subroutine handling, conditional assembly and extended instructions. These features significantly reduce the time required to compose and assem- ble Microcontroller programs.

When combined with standard assembler features such as mnemonic op-codes and address labels, these extended features make MCCAP a powerful pro- gramming tool. After assembling the source input, MCCAP produces an assembly listing and machine- readable object module. MCCAP is also available as a fully supported product from Signetics for use on a user's in-house system.

It assembles both 8X and 8X programs. Also needed is at least one single or double density disk drive with the PROM formatter overlay always residing in drive zero. The 8XAS2 software is contained on three diskettes. Disks 1 and 2 contain the Single Density version and disk 3 contains the Double Density version.

Both versions will be shipped when ordered under this part number. The MCU controls the fetch sequence of microinstructions from the micropro- gram memory. They can be used to modify microinstructions at the outputs of the microprogram memory or to provide additional control lines. The output may also be forced to a logical or logical 1.

It can be used to provide the strobe signal required by interrupt circuits. It can be used to facilitate the implementation of priority interrupt systems. Active high 36 LD Microprogram Address Load Input When the active high state, the microprogram address load input inhibits all jump functions and synchronously loads the data on the instruction buses into the microprogram address register.

However, it does not inhibit the operation of the PR-latch or the generation of the interrupt strobe enable. The functional control of the MCU provides both unconditional jumps to new memory loca- tions and jumps which are dependent on the state of MCU flags or the state of the "PR" latch.

Each intruction has a "jump set" associated with it. This "jump set" is the total group of memory locations which can be ad- dressed by that instruction. The MCU utilizes a two-dimensional address- ing scheme in the microprogram memory. Microprogram memory is organized as 32 rows and 1 6 columns for a total of 51 2 words. Word length is variable according to application. Ad- dress is accomplished by a 9-bit address organized as a 5-bit row and 4-bit column address.

Jump to zero row. AC -AC 3 are used to select 1 of 16 column addresses in row , as the next address. Jump in current row. The current column is specified by MA -MA 3. The PR-latch outputs are asynchronously enabled. The symbols shown below are used to specify row and col- unm addresses. Unconditional Address Control Jump Functions The jump functions use the current micro- program address i. AC -AC 3 are used to select 1 of 16 row addresses in the current row group, specified by MA 8 , as the next row address.

If the current column group, specified by MA 3 , is col -col 7 , the F-latch is used to select col 2 or col 3 as the next column address. If MA 3 specifies column group col 8 -col 15 , the F-latch is used to select col 10 or col-n as the next col- umn address. If the current column group specified by MA 3 is col -col 7 , the C-flag is used to selet col 2 or col 3 as the next column address.

Identical to the JCF function described above, except that the Z-flag, rather than the C-flag, is used to select the next column address. The 4 PR-latch bits are used to select 1 of 16 possible column addresses as the next column address. PR 2 and PR 3 are used to select 1 of 4 column addresses in col 4 through col 7 as the next column address. PR and PR-, are used to select 1 of 4 possi- ble column addresses in col 12 through col 16 as the next column address.

PX 4 -PX 7 are used to select 1 of 16 possible column ad- dresses as the next column address. Function code formats are given in "Flag Control Function summary". The following is a detailed description of each of the 8 flag control functions. Flag Input Control Functions The flag input control functions select which flag or flags will be set to the cur- rent value of the flag input Fl line.

Data on Fl is stored in the F-latch when the clock is low. Flag Output Control Functions The flag output control functions select the value to which the flag output FO line will be forced. The Z-flag is set to the value of Fl. The C-flag is unaffected. Force FO to C. FO is forced to the value of the C-flag. If the LD line is active high at the rising edge of the clock, the data on the primary and secondary instruction buses, PX 4 -PX 7 and SX -SX 3 , is loaded into the microprogram address register.

The high-order bit of the microprogram address register MA 8 is set to a logical 0. The bits from primary instruc- tion bus select 1 of 16 possible column ad- dresses. Likewise, the bits from the secondary instruction bus select 1 of the first 16 row addresses. The line is placed in the active high state whenever a JZR to col 15 is selected as the address control function. The interrupt control responds to the interrupt by puling the enable row address ERA input line low to override the selected next row ad- dress from the MCU.

Then by gating an alter- native next row address on to the row address lines of the microprogram memory, the microprogram may be forced to enter an in- terrupt handling routine. The alternative row address placed on the microprogram memory address lines does not alter the contents of the microprogram address register. Therefore, subsequent jump functions will utilize the row address in the register, and not the alternative row address, to determine the next microprogram addess.

Note, the load function always overrides the address control function on AC -AC 6. In addition, it does not inhibit the interrupt strobe enable or any of the flag con- trol functions. Location indicated by the circled square, represents 1 current row row 2 i and current column col 5 address. The dark boxes indicate the microprogram locations that may be selected by the particular function as the next address.

The N is organized as a 2-bit slice and performs the logical and arithmet- ic functions required by microinstructions. Active low Th roo. Add the result to R n and carry input CI. Deposit the sum in AC and R n. Used to add AC to a register. Deposit the sum in AC or T. Load the result in AC or T, as specified.

Used to load memory data in the specified register, or to load incremented memory data in the specified register. Used to add memory data or incremented memory data to AC and store the sum in the specified register.

Deposit the result in MAR. Add the K-bus to R n and CI. Deposit the result in R n. Conditionally increment R n. Used to maintain a macro-instruction program counter. Conditionally decrement R n by one. Used to force MAR to its highest address and to decrement R n. Add the K-bus to the M-bus and CI. Add CI to the M-bus. Deposit the result in AC or T. Used to load the address register with memory data for macro- instructions using indirect addressing. Subtract one from the M-bus. Used to load decremented memory data in AC or T.

Add the result to the logical AND of specified register with the K-bus. Add the sum to CI. Deposit the result in the specified register. Used to form the 1 's or 2's complement of AC or T. Add CI to the difference and deposit the sum in the specified register. Used to decrement AC or T. Subtract one from the result and add the difference to CI. Deposit the sum in R n. Deposit the sum in AC or T, as specified. Used to condi tionally clear or set AC or T. Deposit the sum in AC or T, as specified Used to load input bus data or decremented input bus data in the specified register.

Add R n and CI to the result. Add the result to CI and the M-bus. Deposit the sum in the specified register. Used to increment AC or T. Add CI to the result and deposit the sum in the specified register. Used to add input data or incremented input data to the specified register.

Logically AND the result with the contents of R n. Deposit the final result in R n. Place the value of the carry OR on the carry output CO line. Force CO to CI. Used to clear a register and force CO to CI. Force CO to one if the result is non-zero. Used to AND the accumulator with a register and test for a zero result.

Deposit the final result in AC ot T. Place the value of the carry OR on CO. Used to clear the specified register and force CO to CI. Used to AND the M-bus data to the accumulator and test for a zero result. Deposit the final result in the specified register.

Used to AND the l-bus to the accumulator and test for a zero result. Used to test a register for zero. Also used to AND K-bus data with a register for masking and, optionally, testing for a zero result. Deposit the result in AC or T, as specified.

Used to load the specified register from memory and test for zero result. Used to test the specified register for zero. Also used to AND the K-bus to the specified register for masking and, optionally, testing for a zero result.

Place the result of the carry OR on CO. Used as a null operation or to force CO to CI. Used to OR the accumulator to a register and, optionally, test the previous accumulator value for zero. Place the carry OR on CO. Deposit the final result in AC or T. Used to load the specified register with memory data and force CO to Ci. Logically AND the K-bus with the l-bus.

Used to OR l-bus data with the specified register and, optionally, test the l-bus data for zero. Exclusive-NOR the result with R n. Used to exclusive-NOR the accumulator with a register. Exclusive NOR the result with the M-bus. Used to exclusive-NOR memory data with the accumulator.

Used to exclusive-NOR input data with the accumulator. This high-speed device provides an efficient means of controlling the flow through a microprogram with a powerful set of sequencing functions. The 8X02A can directly address up to microinstructions; however, the total address space can be ex- panded by adding conventional paging techniques. Combined with memory, the 8X02A forms a powerful control section for CPU's, controllers, test equipment, and other microprogram-controlled systems.

Enable three-state address outputs AQ-Ag ; active-low input. Supply voltage. Clock input positive edge used for all triggering. Active-high condition input used to determine conditional skips, branches, subroutine calls, and loop termination. On the rising edge of the clock input pulse CLK , a new address is latched into the Address Register.

Table 1 defines the eight Address Control Functions. Sequen- tial microprogram flow is provided by the "Increment" INC function which unconditionally increments the Address Register by one for each clock cycle. The Address Register automatically wraps around from the highest address all "1s" to the lowest address all "Os". A Stack Pointer keeps track of the next register of the Stack File to be written into; the pointer is incremented after each "push" and decremented after each "pop" — see Table 1.

To return from a subroutine, the "POP" function pops the return address off the stack and loads it into the Address Register. The "Push-for-Looping" PLP function may be specified in the first instruction of a loop to "push" the current address onto the stack; the Address Register is incremented. If the test for repeating the loop is satisfied TEST input high , the sequencer causes a branch back to the first instruction of the loop in which the top-of-loop address is "pushed" back onto the stack.

If the test fails TEST input low , the top-of-loop address is discarded, the stack pointer is decremented and the Address Reg- ister is incremented. A combination of subroutines and loops may be nested up to four levels deep. In abnormal circumstances, the Stack Pointer will wraparound from the fourth to the first register of the Stack File and vice-versa. If the stack is full four addresses currently stored , an additional "push" causes the first oldest entry to be overwritten — the four most recent entries are always maintained.

If the stack is empty, a "pop" will access the fourth register of the Stack File; however, the contents of this register may be unpredictable. The three-state address outputs Arj-Ag are controlled by a com- mon enable input EN. When the enable input is high, the output drivers are placed in the high-impedance state allowing alternative access to the microprogram memory.

Other circuit functions are unaffected by EN. Pullup resistors should be provided to achieve the required high voltage level. Output Enable Figure 2. All diodes are 1 N or equivalent. In the case of a conditional branch or skip, the status condition applied to the 8X02A TEST input is selected ac- cording to the microinstruction.

In non-branching instructions, this field may contain other CPU control information. When a macroinstruction is presented to the CPU, the starting address of the microprogram routine which executes the macroinstruction is presented to the Branch Address inputs. Similar configurations may be used for other applications in which the Branch Address inputs are typically supplied directly from the microprogram memory.

Dynamic Memory Controller. The serial data stream is divided by a selected polynomial; the remainder resulting from this algebraic process is transmitted at the end of the data stream as a Cyclic Redundancy Check Charac- ter CRCC. At the receiving end, the same calculation is performed on the data. If the received message is error-free, the calculated remainder should satisfy a predetermined pattern.

Eight polynomials are provided and any of these can be selected via a 3-bit control bus. Right justification for polynomials of degree less than 16 is automatic. A binary mes- sage can be interpreted as a binary polynomial H x. During transmission, the remainder is appended to the end of the message as check bits. For a given message, a unique remainder is generated. Hardware implementation of division is simply a feedback shift register with Exclusive-OR gating. Subtrac- tion and addition in modulo 2 is implemented by the Exclusive-OR function.

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